GUC Introduced 5nm HBM3 PHY and Controller Silicon Confirmed at 8.4 Gbps  

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International Unichip Corp. (GUC) 

09.06.2023

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Hsinchu, Taiwan – September 6, 2023 – International Unichip Corp. (GUC), the superior ASIC chief, introduced that they’ve silicon-proven 8.4 Gbps HBM3 resolution on TSMC’s 5nm course of expertise. The platform was demonstrated on the Associate Pavilion of the TSMC 2023 North America Expertise Symposium. It comprises absolutely practical HBM3 Controller and PHY IP and vendor’s HBM3 reminiscence utilizing TSMC’s industry-leading CoWoS® expertise. 

HBM reminiscence distributors hold an aggressive roadmap rising throughput and reminiscence dimension from HBM3 to HBM3E/P and additional doubling knowledge bus width at HBM4. However elementary DRAM timing parameters don’t change and HBM Controller is getting increasingly subtle to allow full bus utilization. GUC’s HBM3 Controller achieves above 90% bus utilization at random entry whereas holding low latency. GUC’s HBM3 PHYs are silicon confirmed at TSMC’s 5nm expertise and had been taped out on the TSMC 3nm early this yr, and able to assist the quickest deliberate HBM3E/P recollections. The PHYs are verified with angle routing of HBM bus on each CoWoS-S and CoWoS-R interposers enabling offsetting HBM PHY vs. HBM reminiscence for ASIC floorplaning flexibility. GUC’s HBM Controller and PHY IPs are utilized in prospects’ HPC ASICs for manufacturing since 2020. 

Explosion within the quantity of computation required from Level4 Autonomous Driving pc results in adoption of two.5D chiplet-based architectures and HBM3 recollections by automobile processors. Harsh automobile atmosphere and excessive reliability requirement make steady monitoring of two.5D interconnect and substitute of failing lanes needed. GUC integrates proteanTecs’ well being and efficiency monitoring options into all its HBM and die-to-die interface check chips. proteanTecs’ expertise is now silicon confirmed in GUC’s 5nm HBM3 PHY, as much as 8.4 Gbps. Throughout knowledge switch in mission mode, I/O sign high quality is repeatedly monitored, with none re-training or interruptions. Every sign lane is individually monitored, permitting for the identification and restore of bump and hint defects earlier than they trigger system operational failures and subsequently extending the chip’s lifetime. “We’re proud to exhibit the world’s first HBM3 controller and PHY at 8.4 Gbps,” stated Dr. Sean Tai, president of GUC. “We established an entire 2.5D/3D chiplet IP portfolio at TSMC’s 7nm, 5nm and 3nm applied sciences. Along with design experience on the TSMC 3DFabric™ applied sciences together with CoWoS, InFO, and TSMC-SoIC, we offer our prospects sturdy and complete resolution of their AI/HPC/xPU/Networking/ADAS merchandise.” 

“Primarily based on high-volume manufacturing expertise of our 2.5D chiplet merchandise we outlined the strictest qualification cycle and lined our IPs with complete set of diagnostics, it permits our IPs to move the hardest high quality standards of the world’s main automobile producers.” stated Igor Elkanovich, CTO of GUC. “Convergence of two.5D and 3D packaging utilizing HBM3, GLink-2.5D/UCIe and GLink-3D interfaces permits extremely modular, chiplet-based, much- bigger-than-reticle-size processors of the long run.” 

To be taught extra about GUC’s HBM3, GLink-2.5D/3D and UCIe IP portfolio and InFO/CoWoS/SoIC complete resolution, please contact your GUC gross sales consultant instantly or ship electronic mail to IP-FAE-AM@guc-asic.com.  

Please go to https://www.guc-asic.com   

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